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FEATURES Low Noise 2.1 nV/Hz Input Voltage Noise 2.1 pA/Hz Input Current Noise Custom Compensation Constant Bandwidth from G = -1 to G = -10 High Speed 200 MHz, (G = -1) 190 MHz, (G = -10) Low Power 34 mW - 6.7 mA Typ for 5 V Supply Output Disable Feature, 1.3 mA Low Distortion -93 dB Second Harmonic, f C = 1 MHz -108 dB Third Harmonic, fC = 1 MHz DC Precision 1 mV Max Input Offset Voltage 0.5 V/ C Input Offset Voltage Drift Wide Supply Range, 5 V to 24 V Low Price Small Packaging Available in SOIC-8 and MICRO_SOIC-8 APPLICATIONS ADC Preamp and Driver Instrumentation Preamp Active Filters Portable Instrumentation Line Receivers Precision Instruments Ultrasound Signal Processing High-Gain Circuits
Low-Noise High-Speed Amplifier for 16-Bit Systems AD8021
CONNECTION DIAGRAM SOIC-8 (R-8) MICRO_SOIC-8 (RM-8)
AD8021
1 2 3 4 8 7 6 5
LOGIC REFERENCE -IN +IN -VS
DISABLE +VS VOUT CCOMP
well-behaved amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast overload recovery of 50 ns. The AD8021 is stable over temperature with low input offset voltage drift and input bias current drift, 0.5 V/C and 10 nA/C respectively. The AD8021 is also capable of driving a 75 line with 3 V video signals. Not only is the AD8021 technically superior but it is also priced considerably less than comparable amps drawing much higher quiescent current. The AD8021 is a high-speed, general-purpose amplifier, ideal for a wide variety of gain configurations, and can be used throughout a signal processing chain and in control loops. The AD8021 is available in both standard 8-lead SOIC and MICRO_SOIC packages in the industrial temperature range of -40C to +85C.
24 VOUT = 50mV p-p 21 18 G = -10, RF = 1k , RG = 100 , RIN = 100 , C C = 0pF G = -5, RF = 1k , RG = 200 , RIN = 66.5 , C C = 1.5pF
PRODUCT DESCRIPTION
The AD8021 is a very high-performance, high-speed, voltage feedback amplifier that can be used in 16-bit resolution systems. It is designed to have low voltage and current noise (2.1 nV/Hz typ and 2.1 pA/Hz typ) while operating at the lowest quiescent supply current (7 mA @ 5 V) among today's high-speed, low-noise op amps. The AD8021 operates over a wide range of supply voltages from 2.5 V to 12 V, as well as from single 5 V supplies, making it ideal for high-speed, low-power instruments. An output disable pin is provided which further reduces quiescent supply current to 1.3 mA. The AD8021 allows the user to choose the gain bandwidth product that best suits the application. With a single capacitor, the user can compensate the AD8021 for the desired gain with little trade-off in bandwidth. The AD8021 is a very REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
CLOSED LOOP GAIN - dB
15 12 9 6 3 0 -3 -6 0.1M 1M 10M FREQUENCY - Hz 100M 1G G = -2, RF = 499 , RG = 249 , RIN = 63.4 , C C = 4pF G = -1, RF = 499 , RG = 499 , RIN = 56.2 , C C = 7pF
Figure 1. Small Signal Frequency Response
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD8021-SPECIFICATIONSVS =S = 5 V FOR V
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Conditions
(@ TA = 25 C, RL = 1 k , Gain = +2, unless otherwise noted.)
Min 355 160 150 110 95 120 250 380 AD8021AR/ARM Typ 490 205 185 150 120 150 300 420 23 50 Max Unit MHz MHz MHz MHz V/s V/s V/s V/s ns ns
Slew Rate, 1 V Step
Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open Loop Gain INPUT CHARACTERISTICS Input Resistance Common Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage--Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio -Power Supply Rejection Ratio
Specifications subject to change without notice.
G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V Step, RL = 500 2.5 V Input Step, G = 2
VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz NTSC, RL = 150 NTSC, RL = 150
-93 -108 -70 -80 2.1 2.1 0.03 0.04 0.4 0.5 7.5 10 0.1 86 10 1 -5.3 to +5.0 -98 -3.8 to +3.4 60 75 15/120 -40 45 50 1.75/1.90 70 2 30 33 2.25 5 7.0 1.3 -95 -95 12.0 7.7 1.6
dBc dBc dBc dBc nV/Hz pA/Hz % Degree mV V/C A nA/C A dB M pF V dB V mA mA pF dB ns ns V A A A A V mA mA dB dB
2.6
1.0 10.5 0.5
TMIN -TMAX +Input or -Input
82
VCM = 4 V
-86 -3.5 to +3.2
VO = 50 mV p-p/1 V p-p f = 10 MHz VO = 0 V to 2 V, 50% Logic to 50% Output VO = 0 V to 2 V, 50% Logic to 50% Output VDISABLE - VLOGIC REFERENCE Logic Ref = 0.4 V DISABLE = 4.0 V Logic Ref = 0.4 V DISABLE = 0.4 V
Output Enabled Output Disabled VCC = +4 V to +6 V, VEE = -5 V VCC = +5 V, VEE = -6 V to -4 V
-86 -86
-2-
REV. 0
unless otherwise SPECIFICATIONS FOR VS = 12 V VS = noted.)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Conditions G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V Step, RL = 500 6 V Input Step, G = 2
(@ TA = 25 C, RL = 1 k , Gain = +2,
AD8021AR/ARM Typ 560 220 200 165 130 170 340 460 21 90
AD8021
Max Unit MHz MHz MHz MHz V/s V/s V/s V/s ns ns
Min 520 175 170 125 105 140 265 400
Slew Rate, 1 V Step
Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage--Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio -Power Supply Rejection Ratio
Specifications subject to change without notice.
VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz NTSC, RL = 150 NTSC, RL = 150
-95 -116 -71 -83 2.1 2.1 0.03 0.04 0.4 0.2 8 10 0.1 88
dBc dBc dBc dBc nV/Hz pA/Hz % Degree mV V/C A nA/C A dB M pF V dB V mA mA pF dB ns ns V A A A A 12.0 8.6 2.0 V mA mA dB dB
2.6
1.0 11.3 0.5
TMIN -TMAX +Input or -Input
84
VCM = 10 V
-86
10 1 -12.2 to +12.0 -96
VO = 50 mV p-p/1 V p-p f = 10 MHz VO = 0 V to 2 V, 50% Logic to 50% Output VO = 0 V to 2 V, 50% Logic to 50% Output VDISABLE - VLOGIC REFERENCE Logic Ref = 0.4 V DISABLE = 4.0 V Logic Ref = 0.4 V DISABLE = 0.4 V
-10.2 to +9.8 -10.6 to +10.2 70 115 15/120 -40 45 50 1.80/1.95 70 2 30 33 2.25 5 7.8 1.7 -96 -100
Output Enabled Output Disabled VCC = +11 V to +13 V, V EE = -12 V VCC = +12 V, VEE = -13 V to -11 V
-86 -86
REV. 0
-3-
FOR V AD8021-SPECIFICATIONSVS =S = +5 V noted.)
Parameter Conditions G = +1, CC = 10 pF, VO = 0.05 V p-p G = +2, CC = 7 pF, VO = 0.05 V p-p G = +5, CC = 2 pF, VO = 0.05 V p-p G = +10, CC = 0 pF, VO = 0.05 V p-p G = +1, CC = 10 pF G = +2, CC = 7 pF G = +5, CC = 2 pF G = +10, CC = 0 pF VO = 1 V Step, RL = 500 0 V to 2.5 V Input Step, G = 2
(@ TA = 25 C, RL = 1 k , Gain = +2, unless otherwise
AD8021AR/ARM Typ 305 190 165 130 110 140 280 390 28 40
Min 270 155 135 95 80 110 210 290
Max
Unit MHz MHz MHz MHz V/s V/s V/s V/s ns ns
DYNAMIC PERFORMANCE
-3 dB Small Signal Bandwidth
Slew Rate, 1 V Step
Settling Time to 0.01% Overload Recovery (50%) DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 HD3 f = 5 MHz HD2 HD3 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Short Circuit Current Capacitive Load Drive for 30% Overshoot DISABLE CHARACTERISTICS Off Isolation Turn-On Time Turn-Off Time DISABLE Voltage--Off/On Enabled Leakage Current Disabled Leakage Current POWER SUPPLY Operating Range Quiescent Current +Power Supply Rejection Ratio -Power Supply Rejection Ratio
Specifications subject to change without notice.
VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p VO = 2 V p-p f = 50 kHz f = 50 kHz
-84 -91 -68 -81 2.1 2.1 0.4 0.8 7.5 10 0.1 76 10 1 0.6 to 5.1 -98 1.10 to 3.60 30 50 10/120 -40 45 50 1.55/1.70 70 2 30 33 2.25 5 6.7 1.2 -82 -84 12.0 7.5 1.5
dBc dBc dBc dBc nV/Hz pA/Hz mV V/C A nA/C A dB M pF V dB V mA mA pF dB ns ns V A A A A V mA mA dB dB
2.6
1.0 10.3 0.5
TMIN -TMAX +Input or -Input
72
1.5 V to 3.5 V
-84 1.25 to 3.38
VO = 50 mV p-p/1 V p-p f = 10 MHz VO = 0 V to 1 V, 50% Logic to 50% Output VO = 0 V to 1 V, 50% Logic to 50% Output VDISABLE - VLOGIC REFERENCE Logic Ref = 0.4 V DISABLE = 4.0 V Logic Ref = 0.4 V DISABLE = 0.4 V
Output Enabled Output Disabled VCC = +4.5 V to +5.5 V, VEE = 0 V VCC = +5 V, VEE = -0.5 V to +0.5 V
-74 -76
-4-
REV. 0
AD8021
ABSOLUTE MAXIMUM RATINGS 1
1.5 TJ = 150 C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V Power Dissipation . . . . . . . . . Observe Power Derating Curves Input Voltage (Common-Mode) . . . . . . . . . . . . . . . VS 1 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . 0.8 V Differential Input Current . . . . . . . . . . . . . . . . . . . . . . 10 mA Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . Observed Power Derating Curves Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The AD8021 inputs are protected by diodes. Current-limiting resistors are not used in order to preserve the low noise. If a differential input exceeds 0.8 V, the input current should be limited to 10 mA.
POWER DISSIPATION - W
8-LEAD SOIC PACKAGE 1.0
8-LEAD SOIC 0.5
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80
90
Figure 2. Maximum Power Dissipation vs. Temperature*
*Specification is for device in free air: 8-Lead SOIC: JA = 160C/W 8-Lead MICRO_SOIC: JA = 200C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8021 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8021 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
PIN CONFIGURATION
LOGIC REFERENCE -IN +IN -VS
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic 1 Logic Reference
Function Reference for Pin 8* Voltage Level. Connect to Logic Low Supply Inverting Input Noninverting Input Negative Supply Voltage Compensation Capacitor. Tie to -VS. (See the Applications section for value.) Output Positive Supply Voltage Disable, Active Low*
2 3 4 5
-IN +IN -VS CCOMP
6 7 8
VOUT +VS DISABLE
1 2 3 4
AD8021
8 7 6 5
DISABLE +VS VOUT CCOMP
*When Pin 8 (DISABLE) is about two or more volts higher than Pin 1 (LOGIC REFERENCE), the part is enabled. When Pin 8 is brought down to within about 1.5 volts of Pin 1, the part is disabled. (See the specification tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part will be in an enabled state.
ORDERING GUIDE
Model AD8021AR AD8021AR-REEL AD8021AR-REEL7 AD8021ARM AD8021ARM-REEL AD8021ARM-REEL7 AD8021AR-EVAL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MICRO_SOIC 8-Lead MICRO_SOIC 8-Lead MICRO_SOIC Evaluation Board
Package Outline SO-8 SO-8 SO-8 RM-8 RM-8 RM-8 SO-8
Branding Information
HNA HNA HNA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8021 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-5-
AD8021 -Typical Performance Characteristics
(TA = 25 C, VS = 5 V, RL = 1 k , G = +2, RF = RG = 499 Freq = 1 MHz, except as otherwise noted.)
24 21 18 CLOSED-LOOP GAIN - dB 15 12 9 G = +2, RF = RG = 499 , C C = 7pF 6 3 0 -3 -6 0.1M G = +1, RF = 75 , C C = 10pF G = +5, RF = 1k , RG = 249 , C C = 2pF GAIN - dB G = +10, RF = 1k , RG = 110 , C C = 0pF
, RS = 49.9
, RO = 976
9
, RD = 53.6
, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,
G = +2 8 7 6 5 4 3 2 VS = 1 0 2.5V 12V VS = 2.5V 5V
1M
10M FREQUENCY - Hz
100M
1G
-1 1M
10M 100M FREQUENCY - Hz
1G
TPC 1. Small Signal Frequency Response vs. Frequency and Gain, VOUT = 50 mV p-p, Noninverting. See Test Circuit 1.
24 21 18 15 G = -10, RF = 1k , RG = 100 , RIN = 100 , C C = 0pF G = -5, RF = 1k , RG = 200 , RIN = 66.5 , C C = 1.5pF
TPC 4. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Noninverting. See Test Circuit 1.
3 G = -1 2 1 0
GAIN - dB
VS =
2.5V 5V
GAIN - dB
12 9 6 3 0 -3 -6 0.1M
-1 -2 -3 -4 -5
VS =
12V
G = -2, RF = 499 , RG = 249 , RIN = 63.4 , C C = 4pF G = -1, RF = 499 , RG = 499 , RIN = 56.2 , C C = 7pF 1M 10M FREQUENCY - Hz 100M 1G
VS = -6 -7 1M
2.5V
10M 100M FREQUENCY - Hz
1G
TPC 2. Small Signal Frequency Response vs. Frequency and Gain, VOUT = 50 mV p-p, Inverting. See Test Circuit 1.
9 G = +2 8 7 6 7pF CC = 5pF
TPC 5. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Inverting. See Test Circuit 3.
9 G = +2 8 7 6 VOUT = 0.1V AND 50mV p-p
GAIN - dB
9pF 4 3 2 1 0 -1 0.1M 1M 10M FREQUENCY - Hz 100M 1G 7pF 9pF
GAIN - dB
5
5 4 VOUT = 4V p-p 3 2 1 0 -1 1M 10M 100M FREQUENCY - Hz 1G 1V p-p
TPC 3. Small Signal Frequency Response vs. Frequency and Compensation Capacitor, VOUT = 50 mV p-p. See Test Circuit 1.
TPC 6. Frequency Response vs. Frequency and VOUT, Noninverting. See Test Circuit 1.
-6-
REV. 0
AD8021
10 G = +2 9 8 7
10 9 8 7
GAIN - dB
G = +2 RF = RG
RF = 1k RF = 499
GAIN - dB
6 5 4 3 2 1 0 0.1M 1M 10M FREQUENCY - Hz 100M 1G RL = 100 1k
6 5 4 3 2 1 0 0.1M RF = 1k 1M AND CF = 2.2pF 100M RF = 150 RF = 75
RF = 250
10M FREQUENCY - Hz
1G
TPC 7. Large Signal Frequency Response vs. Frequency and Load, Noninverting. See Test Circuit 2.
9 G = +2 8 +25 C 7 6
GAIN - dB GAIN - dB
TPC 10. Small Signal Frequency Response vs. Frequency and RF, Noninverting, VOUT = 50 mV p-p. See Test Circuit 1.
15 G = +2 12 9 6
+85 C
5 +85 C 4 3 2 1 0 -1 1M +25 C VOUT = 2V p-p
-40 C
VOUT = 50mV p-p
3 RS = 49.9 0 -3 -6 -9 RS = 100
-40 C
-12
1G
RS = 249
10M 100M FREQUENCY - Hz
-15 0.1M
1M
10M FREQUENCY - Hz
100M
1G
TPC 8. Frequency Response vs. Frequency Temperature and VOUT, Noninverting. See Test Circuit 1.
18 G = +2 15 12
OPEN-LOOP GAIN - dB
TPC 11. Small Signal Frequency Response vs. Frequency and RS, Noninverting. VOUT = 50 mV p-p. See Test Circuit 1.
100
50pF 30pF 20pF
90 80 70 60 50 40 30 20 10 180 135 90 45 0 -45 -90 -135 1G
PHASE - Degrees
9 10pF
GAIN - dB
6 3 0pF 0 -3 -6 -9
-12 1M
10M 100M FREQUENCY - Hz
1G
0 10k
100k
1M 10M FREQUENCY - Hz
100M
TPC 9. Small Signal Frequency Response vs. Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p. See Test Circuit 2 and Figure 16.
TPC 12. Open-Loop Gain and Phase vs. Frequency. RG =100 , RF = 1 k, RO = 976 , RD = 53.6, CC = 0 pF. See Test Circuit 3.
REV. 0
-7-
AD8021
6.4 G = +2 -30 6.2 VS = 2.5V -50 -40 -20
f1 f = 0.2MHz
f2
POUT 976 53.6 50
POUT - dBm
12V
GAIN - dB
6.0 5V 5.8
-60 -70 -80 -90
5.6
-100 -110
5.4 1M
10M FREQUENCY - Hz
100M
-120 9.5
9.7
10 FREQUENCY - MHz
10.3
10.5
TPC 13. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p, RL = 150 . Noninverting, See Test Circuit 2.
-20 -30 -40 -50
DISTORTION - dBc
TPC 16. Intermodulation Distortion vs. Frequency
50
THIRD ORDER INTERCEPT - dBm
45
-60 -70 -80 -90 -100 -110 -120 -130 0.1M -3RD RL = 100 RL = 1k 2ND
40 VS = VS = 30 2.5V 5V
35
25
20 1M FREQUENCY - Hz 10M 20M 0 5 10 FREQUENCY - MHz 15 20
TPC 14. Second and Third Harmonic Distortion vs. Frequency and R L
-30 -40
TPC 17. Third Order Intercept vs. Frequency and Supply Voltage
-50 -60
-50
DISTORTION - dBc
DISTORTION - dBc
-60 -70 -80 -90 -100 -110 -120 -130 100k 2ND 2ND VS = 5V 3RD VS = 12V VS = 2.5V 2ND 3RD 3RD
-70 2ND -80 -90 2ND -100 -110 3RD -120 1 2 4 3 VOUT - V p-p 5 6 RL = 1k 3RD RL = 100
1M FREQUENCY - Hz
10M
20M
TPC 15. Second and Third Harmonic Distortion vs. Frequency and VS
TPC 18. Second and Third Harmonic Distortion vs. VOUT and RL
-8-
REV. 0
AD8021
-50 -60 -70
DISTORTION - dBc
3.5 3.4 -3.1 -3.2 POSITIVE OUTPUT 3.3 3.2 3.1 3.0 2.9 2.8 0 400 1200 800 LOAD - 1600 -3.3 -3.4 -3.5 -3.6 -3.7 -3.8 2000
2ND
fC = 5MHz
-80 3RD -90 2ND -100 -110 -120 1 2 4 3 VOUT - V p-p 5 6
fC = 1MHz
3RD
NEGATIVE OUTPUT
TPC 19. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fC), G = +2
-40 -50 -60
TPC 22. DC Output Voltage vs. Load. See Test Circuit 1.
120
DISTORTION - dBc
2ND
SHORT-CIRCUIT CURRENT - mA
fC = 5MHz
100
VS =
12
80
VS =
5.0
-70 3RD -80 2ND -90 -100 -110 1 2 4 3 VOUT - V p-p 5 6 3RD
60 VS = 40 2.5
fC = 1MHz
20
0 -50
-30
-10
10 30 50 TEMPERATURE - C
70
90
110
TPC 20. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fC), G = +10
-70
TPC 23. Short-Circuit Current to Ground vs. Temperature
50 G = +2 40 30 20
VOUT - mV
fC = 1MHz
RL = 1k -80
DISTORTION - dBc
RL = 1k , 150
-90 2ND -100
10
-10 -20
3RD -110
-30 -40
-120 0 200 400 600 FEEDBACK RESISTANCE - 800 1000
-50 0 40 80 120 TIME - ns 160 200
TPC 21. Second and Third Harmonic Distortion vs. Feedback Resistor (RF)
TPC 24. Small Signal Transient Response vs. RL, VO = 50 mV p-p. See Test Circuit 2, Noninverting.
REV. 0
-9-
NEGATIVE OUTPUT VOLTAGE - V
POSITIVE OUTPUT VOLTAGE - V
AD8021
2.0 VO = 4V p-p G = +2
2.0
VO = 2V p-p G = +2
RL = 1k 1.0
1.0
VOUT - V
RL = 150
VOUT - V
VS =
2.5V
-1.0
-1.0 VS = 5V
-2.0
-2.0
0 40 80 120 TIME - ns 160 200
0
40
80
120 TIME - ns
160
200
TPC 25. Large Signal Transient Response vs. RL. See Test Circuit 2, Noninverting.
5 4 3 2 1
VOLTS
TPC 28. Large Signal Transient Response vs. VS. See Test Circuit 1.
VIN = 3V G = +2 VIN = 1V/DIV VOUT = 2V/DIV
VO = 4V p-p G = -1
VOUT, RL = 1k
VIN
RL = 150
-1 -2 -3 -4
VIN
VOUT
-5 0 50 100 150 TIME - ns 200 250
0 100 200 300 TIME - ns 400 500
TPC 26. Large Signal Transient Response. See Test Circuit 3, Inverting.
CL = 50pF G = +2 VO = 4V p-p
TPC 29. Overdrive Recovery vs. RL. See Test Circuit 2.
G = +2
2.0
OUTPUT SETTLING
1.0
VOUT - V
CL = 10pF, 0pF
+0.01%
-0.01% 25ns
-1.0
-2.0
VERT = 0.2mV/DIV
0 40 80 120 TIME - ns 160 200
HOR = 5ns/DIV
TPC 27. Large Signal Transient Response vs. CL. See Test Circuit 1.
TPC 30. 0.01% Settling Time, 2 V Step
-10-
REV. 0
AD8021
50 40 30 20 G = +1
0.48
0.44
VOLTAGE OFFSET - mV
0 40 80 120 TIME - ns 160 200
0.40
VOUT - mV
10
0.36
-10 -20 -30 -40 -50
0.32
0.28
0.24 -50
-25
25 50 0 TEMPERATURE - C
75
100
TPC 31. Small Signal Transient Response, VO = 50 mV p-p . G = +1. See Test Circuit 1.
100
TPC 34. VOS vs. Temperature
8.4
8.0
INPUT BIAS CURRENT - A
1M 10M
VOLTAGE NOISE - nV/ Hz
7.6
10
7.2
6.8
2.1nV/ Hz
6.4
1 10
100
1k
10k 100k FREQUENCY - Hz
6.0 -50
-25
0 25 50 TEMPERATURE - C
75
100
TPC 32. Input Voltage Noise vs. Frequency
100
TPC 35. Input Bias Current vs. Temperature
-20 -30
INPUT CURRENT NOISE - pA/ Hz
-40 -50
CMRR - dB
-60 -70 -80 -90
10
-100 -110 1 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M -120 10k 100k 1M FREQUENCY - Hz 10M 100M
TPC 33. Input Current Noise vs. Frequency
TPC 36. CMRR vs. Frequency. See Test Circuit 4.
REV. 0
-11-
AD8021
300 100 30 300k 100k 30k
OUTPUT IMPEDANCE -
OUTPUT IMPEDANCE -
10 3 1 0.3 0.1 0.03 0.01
10k 3k 1k 300 100 30 10 3 10k
0.003 10k
100k
1M 10M FREQUENCY - Hz
100M
1G
100k
1M 10M FREQUENCY - Hz
100M
1G
TPC 37. Output Impedance vs. Frequency, Chip Enabled. See Test Circuit 5.
DISABLE 4V 2V
TPC 40. Output Impedance vs. Frequency, Chip Disabled. See Test Circuit 8.
0 -10 -20 -30 -PSRR
VOUTPUT 2V
PSRR - dB
-40 -50 -60 -70 VS = 2.5V +PSRR VS = 12V
tEN = 45ns
1V
tDIS = 50ns
-80 -90 -100 10k
VS =
5V
0
100
200 300 TIME - ns
400
500
100k
1M 10M FREQUENCY - Hz
100M
500M
TPC 38. Enable (tEN)/Disable (tDIS) Time vs. VOUT. See Test Circuit 6.
0 -10 -20
TPC 41. PSRR vs. Frequency and Supply Voltage. See Test Circuits 9 and 10.
8.5
8.0
DISABLED ISOLATION - dB
-30 -40 -50 -60 -70 -80 -90 -100 0.1M 1M 10M FREQUENCY - Hz 100M 1G
SUPPLY CURRENT - mA
7.5
7.0
6.5
6.0
5.5 -50
-25
0 25 50 TEMPERATURE - C
75
100
TPC 39. Input to Output Isolation, Chip Disabled. See Test Circuit 7.
TPC 42. Quiescent Supply Current vs. Temperature
-12-
REV. 0
AD8021
TEST CIRCUITS
HP8753D NETWORK ANALYZER
50
+VS RO 5 RIN 49.9 CC -VS RG RF RD 50 CABLE
50
50 50
CABLE
AD8021
499 499 CC -VS 55.6 499 7pF 499 +VS 5
RS
49.9
CF
Test Circuit 1. Noninverting Gain Test Circuit
Test Circuit 4. CMRR Test Circuit
50 50
CABLE
+VS RS
FET PROBE
AD8021
+VS
HP8753D NETWORK ANALYZER
5 RIN 49.9 -VS RG CC RF
100
CL RL
5 CC 7pF -VS
50
RG 499
RF 499
CF
Test Circuit 2. Noninverting Gain Test Circuit with FET Probe
Test Circuit 5. Output Impedance, Chip Enabled
AD8021
+VS RO 49.9 CC 50 50 CABLE RIN 49.9 RG -VS RF 5 RD 50 CABLE
49.9 1.0V 49.9 1
+VS 976 5 53.6
LOGIC REF 8 DISABLE
4V
49.9 -VS 499 499
CC 7pF
Test Circuit 3. Inverting Gain Test Circuit
Test Circuit 6. Enable/Disable Test Circuit
REV. 0
-13-
AD8021
HP8753D NETWORK ANALYZER BIAS BNC 50 50 50 50 +VS 49.9 49.9 1 CABLE +VS 249 5 1k -VS 499 CC 7pF 499 49.9 , 5W 976 5 53.6 +VS HP8753D NETWORK ANALYZER 50
50
CABLE
AD8021
LOGIC REF 8 DISABLE CC 7pF
FET PROBE
-VS 499 499
Test Circuit 7. Input to Output Isolation, Chip Disabled
Test Circuit 9. Positive PSRR
BIAS BNC
HP8753D NETWORK ANALYZER 50 50 50 +VS CABLE
AD8021
1 8 100 +VS 50
HP8753D NETWORK ANALYZER
-VS
5 CC 7pF -VS
976 249 5 CC 7pF 53.6
-VS 49.9 5W
499
499
Test Circuit 8. Output Impedance, Chip Disabled
Test Circuit 10. Negative PSRR
-14-
REV. 0
AD8021
USING THE AD8021
COMPENSATION CAPACITANCE - pF
The typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, CINTERNAL, using "dominant pole compensation." To a first-order approximation, voltage feedback op-amps have a fixed Gain Bandwidth Product; for example, if its -3 dB bandwidth for G = +1 is 200 MHz, at a gain of G = +10, its bandwidth will be only about 20 MHz. The AD8021 is a voltage feedback op amp with a minimal CINTERNAL of about 1.5 pF. By adding an external compensation capacitor, CC, the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. Unlike the typical op amp with fixed compensation, the AD8021 allows the user to: 1. Maximize the amplifier bandwidth for closed-loop gains between 1 and 10, avoiding the usual loss of bandwidth and slew-rate. 2. 3. Optimize the trade-off between bandwidth and phase margin for a particular application. Match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in Figure 11 of the Applications section).
110 100 90 86 80 70 60 50 40 30 20 10 0 (A) -10 1k 10k 100k 1M 10M 100M FREQUENCY - Hz 1G 10G (B) (C) CC = 10pF 180 135 90 CC = 0pF (B) (A) (C) 45
PHASE - Degrees
bandwidth is degraded to about 20 MHz, and the phase margin increases to 90 (Arrow B). However, by reducing CC to zero, the bandwidth and phase margin return to about 200 MHz and 60 (Arrow C), respectively. In addition, the slew rate is dramatically increased, as it roughly varies with the inverse of C C.
10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 NOISE GAIN - V/V 8 9 10 11
Figure 4. Suggested Compensation Capacitance vs. Gain for Maintaining 1 dB Peaking
OPEN-LOOPGAIN - dB
0
Table I and Figure 4 provide lists recommended values of compensation capacitance at various gains, and the corresponding slew rate, bandwidth, and noise. Note that the value of the compensation capacitor depends on the circuit noise gain, not voltage gain. As shown in Figure 5, the noise gain, GN, of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or noninverting gain. Thus, Noninverting GN = RF/RG +1 Inverting GN = RF/RG +1
RS 3 + 6 5 RF 800 3+ -VS RG 200 CCOMP INVERTING RG 200 2 RF 800
1
Figure 3. Simplified Diagram of AD8021 Open-Loop Gain and Phase Response
AD8021
2- -VS CCOMP G = GN = 5
-
AD8021
5
6
Figure 3 is the AD8021 gain and phase plot that has been simplified for instructional purposes. If the desired closed-loop gain is G = +1, and CC = 10 pF is chosen, Arrow "A" of the figure shows that the bandwidth is about 200 MHz and the phase margin is about 60. If the gain is changed to G = +10 and CC fixed at 10 pF, then (as expected for a typical op amp), the
G = -4 GN = 5
NONINVERTING
Figure 5. The Noise Gain of Both Is Five
Table I. Recommended Component Values. See Test Circuit 2. C F = CL = 0, RL = 1 k , RIN = 49.9
Noise Gain (Noninverting Gain) 1 2 5 10 20 100 REV. 0
RS () 75 49.9 49.9 49.9 49.9 49.9
RF () 75 499 1k 1k 1k 1k
RG () NA 499 249 110 52.3 10
CCOMP (pF) 10 7 2 0 0 0
Slew Rate (V/ s) 120 150 300 420 200 34 -15-
-3 dB SS BW (MHz) 490 205 185 150 42 6
Output Noise (AD8021 Only) (nV/ Hz ) 2.1 4.3 10.7 21.2 42.2 211.1
Output Noise (AD8021 with Resistors) (nV/ Hz ) 2.8 8.2 15.5 27.9 52.7 264.1
AD8021
With the AD8021, a variety of trade-offs can be made to finetune its dynamic performance. Sometimes more bandwidth or slew rate is needed at a particular gain. Reducing the compensation capacitance, as illustrated in TPC 3, will increase the bandwidth and peaking due to a decrease in phase margin. On the other hand, if more stability is needed, increasing the compensation cap will decrease the bandwidth while increasing the phase margin. As with all high-speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. Often the input capacitance (due to the op amp itself as well as the pc board) could have a significant effect. The feedback resistance, together with the input capacitance, may contribute to a loss of phase margin, thereby affecting the high-frequency response, as shown in TPC 10. As further shown, a capacitor (CF) in parallel with the feedback resistor can compensate for this phase loss. Additionally, any resistance in series with the source will create a pole with the input capacitance (as well as dampen high-frequency resonance due to package and board inductance and capacitance), the effect of which is shown in TPC 11. It must also be noted that increasing resistor values will increase the overall noise of the amplifier, and that reducing the feedback resistor value will increase the load on the output stage, thus increasing distortion (TPC 18).
Using the Disable Feature
Two internal diode-clamps across the inputs (pins 2 and 3) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset-voltage and input bias current.
+VS
OUTPUT +IN
CINTERNAL 1.5pF -IN -VS CCOMP CC
Figure 6. Simplified Schematic
PCB LAYOUT CONSIDERATIONS
When Pin 8 (DISABLE) is about two or more volts higher than Pin 1 (LOGIC REFERENCE), the part is enabled. When Pin 8 is brought down to within about 1.5 volts of Pin 1, the part is disabled. (See the specification tables for exact disable and enable voltage levels). If the disable feature is not going to be used, Pin 8 can be tied to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part will be in an enabled state.
THEORY OF OPERATION
As with all high-speed op amps, achieving optimum performance from the AD8021 requires careful attention to PC board layout. Particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. Otherwise, lead inductance can influence the frequency response and even cause high frequency oscillations. Use of a multilayer printed circuit board, with an internal ground plane, will reduce ground noise and enable a compact component arrangement. Due to the relatively high impedance of Pin 5, and low values of the compensation capacitor, a guard ring is recommended. The guard ring is simply a PC trace that encircles Pin 5 and is connected to the output, Pin 6, which is at the same potential as Pin 5. This serves two functions. It shields Pin 5 from any local circuit noise generated by surrounding circuitry. It also minimizes stray capacitance, which would tend to otherwise reduce the bandwidth. An example of a guard ring layout may be seen in Figure 7. Also shown in Figure 7, the compensation capacitor is located immediately adjacent to the edge of the AD8021 package, spanning Pin 4 and Pin 5. This capacitor must be a high-quality surface-mount COG or NPO ceramic. The use of leaded capacitors is not recommended. The high-frequency bypass capacitor(s) should be located immediately adjacent to the supplies, Pins 4 and 7. To achieve the shortest possible lead length at the inverting input, the feedback resistor RF is located beneath the board and just spans the distance from the output, Pin 6, to inverting input Pin 2. The return node of resistor RG should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to Pin 4.
The AD8021 is fabricated on the second generation of Analog Devices' proprietary High Voltage eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fT's in the 3 GHz region. The transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. It also reduces the nonlinear capacitance (a source of distortion), and allows a higher transistor fT for a given quiescent current. The supply current is trimmed, which results in less part-to-part variation of bandwidth, slew rate, distortion, and settling time. As shown in Figure 6, the AD8021 input stage consists of an NPN differential pair in which each transistor operates at 0.8 mA collector current. This allows the input devices a high transconductance and hence, the AD8021 has a low input noise of 2.1 nV/Hz @ 50 kHz. The input stage drives a folded cascode that consists of a pair of PNP transistors. The folded cascode and current mirror provide a differential to single-ended conversion of signal current. This current then drives the high-impedance node (Pin 5), where the CC external capacitor is connected. The output stage preserves this high impedance with a current gain of 5,000, so that the AD8021 can maintain a high open-loop gain, even when driving heavy loads.
-16-
REV. 0
AD8021
(TOP VIEW) LOGIC REFERENCE 1 8 +VS 7 VOUT GROUND PLANE -VS METAL BYPASS CAPACITOR COMPENSATION CAPACITOR GROUND PLANE 4 5 CCOMP DISABLE BYPASS CAPACITOR
Table II. Summary of ADC Driver Performance, fC = 65 kHz, VOUT = 10 V p-p
Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR
Measurement -101.3 -109.5 -100.0 100.3
Unit dB dB dB dB
-IN
2
+IN
3
6
Figure 9 shows another ADC driver connection. The circuit was tested with a noninverting gain of 10.1 and an output voltage of approximately 20 V p-p, for optimum resolution and noise performance. No filtering was used. An FFT was performed using Analog Devices' evaluation software for the AD7665 16-bit converter. The results are listed in Table III.
+12V 50 50 5V 3+ 6 5 - CC RF 750 IN HI
Figure 7. Recommended Location of Critical Components and Guard Ring
DRIVING 16-BIT ADC CONVERTERS
50 2
AD8021
-12V RG 82.5
AD7665
570 kSPS ADC
As seen in TPC 15, the harmonic distortion is better than 90 dB at frequencies between 100 kHz and 1 MHz. This is a real advantage for complex waveforms that contain highfrequency information, as the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. The increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a `sample.' This advantage is particularly apparent when using 16-bit high-resolution A-to-D converters, with high sampling rates. Figure 8 shows a typical ADC driver configuration. The AD8021 is in an inverting gain of -7.5, fC is 65 kHz, and its output voltage is 10 V p-p. The results are listed in Table II.
+12V 3 590 2 RG 200 50 65kHz 5V + 6 5 - CC 10pF -12V RF 1.5k 56pF IN HI
OPTIONAL CF
IN LO
Figure 9. Noninverting ADC Driver, Gain = 10, fC = 100 kHz
Table III. Summary of ADC Driver Performance, fC = 100 kHz, VOUT = 20 V p-p
Parameter Second Harmonic Distortion Third Harmonic Distortion THD SFDR
DIFFERENTIAL DRIVER
Measurement -92.6 -86.4 -84.4 5.4
Unit dB dB dB dB
AD8021
AD7665
570 kSPS
The AD8021 is uniquely suited as a low-noise differential driver for many ADCs, balanced lines, and other applications requiring differential drive. If pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter will be higher than that of the follower section, resulting in an imbalance in the frequency response (see Figure 11). A better solution takes advantage of the external compensation feature of the AD8021. By reducing the CCOMP value of the inverter, its bandwidth may be increased to match that of the follower, avoiding compromises in gain bandwidth and phase delay. The inverting and noninverting bandwidths can be closely matched using the compensation feature, thus minimizing distortion.
IN LO
Figure 8. Inverting ADC Driver, Gain = -7.5, fC = 65 kHz
REV. 0
16 BITS
-17-
16 BITS
Low noise and adjustable compensation make the AD8021 especially suitable as a buffer/driver for high-resolution A-to-D converters.
AD8021
Figure 10 illustrates an inverter-follower driver circuit operating at a gain of two, using individually compensated AD8021s. The values of feedback and load resistors were selected to provide a total load of less than 1 k, and the equivalent resistances seen at each op amp's inputs were matched in order to minimize offset voltage and drift. Figure 12 is a plot of the resulting ac responses of driver halves.
VIN 49.9 249 3+ G = +2 6 5 - -VS 499 7pF 499 1k 232 3+ G = -2 6 5 - -VS 332 5pF 664 1k
VIN R1 R2 3 2 CC -VS RG RF
USING THE AD8021 IN ACTIVE FILTERS
AD8021
2
The low noise and high gain bandwidth of the AD8021 make it an excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters, but neglects the effect of the op amp's finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. Unfortunately, real filters do not behave in this manner. Instead, they exhibit finite limits of attenuation, dependent on the gain bandwidth of the active device. Good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency passband performance. Figure 13 shows the schematic of a 2-pole, low-pass active filter, and Table IV lists typical component values for filters having a Bessel-type response with gains of 2 and 5. Figure 14 is a network analyzer plot of this filter's performance.
C1 +VS
VOUT1
AD8021
2
VOUT2
AD8021
6 5 VOUT
C2
Figure 10. Differential Amplifier
12 9 6 3
GAIN - dB
Figure 13. Schematic of a Second Order Low-Pass Active Filter
G = -2 G = +2
0 -3 -6 -9
Table IV. Typical Component Values for Second Order LowPass Filter of Figure 13
Gain R1 ( ) R2 ( ) RF ( ) RS ( ) C1 2 5 71.5 44.2
50 1M 10M FREQUENCY - Hz 100M 1G 40 30 20 G=5
C2
CC 7 pF 2 pF
-12 -15 -18 100k
215 365
499 90.9
499 365
10 nF 10 nF 10 nF 10 nF
Figure 11. AC Response of Two Identically Compensated High-Speed Op Amps Configured for Gain of +2 and -2
12 9 6
GAIN - dB
10 0 G=2 -10 -20
3 G= 2
-30 -40
GAIN - dB
0 -3 -6 -9
-50 1k
10k
100k FREQUENCY - Hz
1M
10M
-12 -15 -18 100k 1M 10M FREQUENCY - Hz 100M 1G
Figure 14. Frequency Response of the Filter Circuit of Figure 13 for Two Different Gains.
Figure 12. AC Response of Two Dissimilarly Compensated AD8021 Op Amps (Figure 11) Configured for Gain of +2 and -2. Note the Close Gain Match.
-18-
REV. 0
AD8021
Driving Capacitive Loads
20 18 16 14 12
RSNUB -
When the AD8021 drives a capacitive load, the high frequency response may show excessive peaking before it rolls off. Two techniques can be used to improve stability at high frequency and reduce peaking. The first technique is to increase the compensation capacitor, CC, which reduces the peaking while maintaining gain flatness at low frequencies. The second technique is to add a resistor, RSNUB, in series between the output pin of the AD8021 and the capacitive load, CL. Figure 15 shows the response of the AD8021 when both CC and RSNUB are used to reduce peaking. For a given CL, Figure 16 can be used to determine the value of RSNUB that maintains 2 dB of peaking in the frequency response. Please note, however, that using RSNUB attenuates the low-frequency output by a factor of RLOAD/(RSNUB + RLOAD).
18 +VS 16 14 12
GAIN - dB
10 8 6 4 2 0 0 5 10 15 20 25 30 35 CAPACITIVE LOAD - pF 40 45 50
49.9 49.9 -VS 499 CC 499
FET PROBE 5 RSNUB 6 33pF RL 1k
CC = 7pF; RSNUB = 0 CC = 8pF; RSNUB = 0
Figure 16. Relationship of RSNUB vs. CL for 2 dB Peaking at a Gain of +2
10 8 6 4 2 0 0.1
CC = 8pF; RSNUB = 17.4 1 10 FREQUENCY - MHz 100 1000
Figure 15. Peaking vs. RSNUB and CC for CL = 33 pF
REV. 0
-19-
AD8021
EVALUATION BOARD
A SOIC evaluation board is available for the AD8021. The board provides both an inverting and noninverting circuit topology.
Evaluation Board Applications
In the differential configuration, either of the input SMA connectors may be used and the amplifier inputs connected with R22 and R23. Resistors R9, R10, R14, and R15 may be omitted if the default disable mode is used. Either amplifier may be disabled from an external source. Zero resistors R4, R19, R21, and R23 may be removed to disable one of the amplifiers. For gains of less than 10, refer to Figure 4 and Table I for the value of the compensation capacitors C6 and C13.
Referring to the schematic of Figure 17, separate SMA input connectors and termination resistors are provided for noninverting and inverting amplifiers. Separate amplifiers may be used as a differential amplifier as in Figure 10.
R26 0 R8 0 R7 1 2 +VIN SMA R23 0 R6 49.9 R25 0 C1 0.1 F R22 0 -VIN SMA R20 49.9 R8 0 C15 10 F + R21 0 R11 R4 1 2 LOGIC REF -IN R1 DIS +VS VOUT CCOMP 8 7 6 C7 1nF C14 0.1 F R16 INV. AMPLIFIER R14 0 R15 0 R1 3 4 -VS CCOMP LOGIC REF -IN +IN DIS +VS 6 VOUT 5 C8 R2 R3 8 7 C3 1nF NON-INV. AMPLIFIER R1 R10 0 R9 0
DISABLE
R4 0 +VS C4 0.1 F +OUT
AD8021
C2 1nF
C6
C5
R18 0
+ C16 10 F
R19 0
-VS
3 +IN 4
AD8021
-OUT 5 C11 R13 R12
-VS
C9 0.1 F
C10 1n F
C13
C12
TP1 -VS GND
+VS
P1
Figure 17. Schematic of AD8021 Evaluation Board
-20-
REV. 0
AD8021
Figure 18. Evaluation Board Silkscreen (Top)
Figure 20. Evaluation Board Layout (Bottom)
Figure 19. Evaluation Board Layout (Top)
Figure 21. Evaluation Board Silkscreen (Bottom)
REV. 0
-21-
AD8021
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (R-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
8-Lead MICRO_SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27
0.028 (0.71) 0.016 (0.41)
-22-
REV. 0
-23-
-24-
C01888-1.5-7/01(0)
PRINTED IN U.S.A.

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